This is a demonstration page for the DigitalJS digital logic simulator and the yosys2digitaljs netlist format converter, by Marek Materzok, University of Wrocław. The source files are on Github. Contributions are welcome! This demo was made possible by the Yosys open-source hardware synthesis framework.
Enter your SystemVerilog code, or load an example by using the dropdown menu, and press the button to start the simulation.