This is a demonstration app for the DigitalJS digital logic simulator and the yosys2digitaljs netlist format converter, by Marek Materzok, University of Wrocław. The source files are on Github. Contributions are welcome! This was made possible by the Yosys open-source hardware synthesis framework.
Create a new tab and enter your SystemVerilog code, or load an example by using the dropdown menu, and press the Synthesize button to start the simulation.